In general, image sensors are semiconductor devices that transform an optical image to electrical signals. Among the types of image sensors, a CMOS (complementary-metal-oxide-semiconductor) image sensor has adapted a switch mode by forming transistors for each unit pixel with a CMOS technology, and using control circuits and signal-processing circuits in conjunction with the transistors to sequentially detect outputs.
Efforts are continually being made to improve the photosensitivity of the image sensor.
For example, the CMOS image sensor is composed of a photodiodes for sensing light and a CMOS logic circuit for processing the sensed light into electric signals to convert them to data. For better photosensitivity, two methods have been proposed. In a first method, efforts are used to increase an occupied area of the photodiode with respect to the total area of the image sensor. In a second method, technologies are used to reduce an incident path of light, to form a microlens at an upper portion thereof, and to receive more light in a photodiode region.
The CMOS image sensor is classified as a 3T type, a 4T type or a 5T type according to the number of transistors formed in a unit pixel. The 3T type CMOS image sensor includes a single photodiode and three transistors, and the 4T type CMOS image sensor includes a single photodiode and four transistors. The 3T CMOS image sensor will now be described with reference to an equivalent circuit diagram and a layout thereof.
FIG. 1 is an equivalent circuit diagram of a 3T type CMOS image sensor according to the related art. FIG. 2 is a layout view showing a unit pixel of the 3T type CMOS image sensor.
As shown in FIG. 1, the unit pixel of the typical 3T CMOS image according to the related art includes one photodiode (PD) and three NMOS transistors T1, T2 and T3. The photodiode includes a cathode connected to the drain of the first NMOS transistor T1 and the gate of the second NMOS transistor T2.
Further, the sources of the first and second NMOS transistors T1 and T2 are connected to a power line that supplies a reference voltage, and the gate of the first NMOS transistor T1 is connected to a reset line that supplies a reset signal.
The source of the third NMOS transistor T3 is connected to the drain of the second NMOS transistor, and the drain of the third NMOS transistor T3 is connected to a reading circuit (not shown) through a signal line. The gate of the third NMOS transistor T3 is connected to a column selection line that supplies a selection signal SLCT.
Accordingly, the first NMOS transistor T1 functions as a reset transistor Rx, the second NMOS transistor T2 functions as a driver transistor DX, and the third NMOS transistor T3 functions as a selection transistor Sx.
As shown in FIG. 2, an active region 10 is defined for a general unit pixel of the 3T CMOS image sensor. One photodiodes 20 is formed at a wider part of the active region 10. Three gate electrodes 120, 130, 140 of the transistors overlap the remaining parts of the active region 10.
FIGS. 3A through 3F are cross-sectional views for describing a method for manufacturing a CMOS sensor having a vertical photodiodes construction according to the related art.
Referring to FIG. 3A, a pixel array 32 is formed by selectively implanting impurity ions in a semiconductor substrate 31 at a photodiode region. The pixel array 32 includes photodiodes, which are formed at the semiconductor substrate 31 to different depths and sense red (R), green (G), and blue (B) signals, respectively.
Next, a device (not shown) for processing signals and a multilayer metal wire (not shown) are sequentially formed on the semiconductor substrate 31 in which the pixel array 32 is formed. The multilayer metal wire functions to connect respective parts to each other.
Then, an interlayer dielectric 33 is formed at an entire surface of the semiconductor substrate 31. An oxide layer is formed on the interlayer dielectric 33 to obtain a passivation layer 34 in order to protect the device from moisture or an externally physical shock.
Referring to FIG. 3b, after a photoresist 35 is coated on the passivation layer 34, the photoresist 35 is selectively patterned to expose an upper portion of the pixel array 32 by exposure and developing processes.
As shown in FIG. 3C, the passivation layer 34 formed at an upper portion of the pixel array 32 is selectively removed using the patterned photoresist 35 as a mask.
The process for selectively removing the passivation layer 34 includes a pad opening process for exposing a metal pad, which is formed at a pad region of the semiconductor substrate 31.
Referring to FIG. 3D, the photoresist 35 is removed, and an interlayer dielectric 33 disposed at an upper portion of the pixel array 32 is selectively removed through a dry etch by performing photolithography and etch processes, thereby forming a trench 36 to a predetermined depth from a surface of the interlayer dielectric.
As shown in FIG. 3E, a photoresist layer 37a for a microlens is coated on an entire surface of the semiconductor substrate 31.
Referring to FIG. 3F, after the photoresist layer 37a for a microlens is selectively patterned, a reflow process is performed to form a plurality of microlenses 37 at predetermined intervals on the interlayer dielectric 33 in the trench 36.
However, in the conventional method for manufacturing the semiconductor device, as shown in FIG. 3E, the interlayer dielectric 33 and the passivation layer 34 disposed at a side of the trench 36 have a vertical profile when coating the photoresist layer 37a. Accordingly, the photoresist layer 37a is not coated with uniform thickness and causes striation.